Deploying and extending a RISC-V CPU

Cybersecurity bachelor project by Leon Trampert. The goals were to explore existing open-source RISC-V CPU (and SoC) designs, their deployment requirements, and the possibility to implement own CPU extension. In particular, Leon has explored the Rocket Chip and lowRISC projects and successfully deployed them on a Nexys A7 FPGA development board. In addition, he explored how to extend a Rocket Core CPU with custom coprocessor instructions.

I have co-supervised the project with Prof. Dr. Christian Rossow. My responsibilities have been to guide Leon Tramper throughout the project, define the goals and working tasks, and provide him with technical advice and the required resources.